The present invention relates to a PLL circuit.
A PLL apparatus which generates, from a reference signal having a certain frequency, signals having various frequencies that are in synchronization with this reference signal is known as illustrated in xe2x80x9cSANYO TECHNICAL REVIEWxe2x80x9d VOL.10, NO.1, page 32, February 1978, for example. This PLL apparatus includes a reference oscillator generating a reference signal RF, a voltage-controlled oscillator generating an output signal OF having a frequency responsive to a control voltage CV, a variable frequency divider dividing the output signal OF to produce a feedback signal FV, a single phase comparator comparing the phase of the feedback signal FV with the phase of the reference signal to produce an error signal ER, and a low-path filter producing the control voltage CV in response to the error signal ER.
This PLL circuit has the disadvantage of having a long lock-up time (the time until synchronization between the output signal and the reference signal is reached), since it has a single-stage phase comparator and therefore, phase comparison is performed only once during one period of the reference signal.
Japanese Unexamined Patent Publication No. 10-135822 discloses a PLL circuit which can get rid of such disadvantage. The PLL circuit disclosed in this publication includes means for generating a plurality of reference signals having different phases, a plurality of (four, for example) frequency dividers for dividing the frequency of the output signal of the voltage-controlled oscillator, and a plurality of phase comparators for comparing the phase of each of the frequency dividers with the phase of a corresponding one of the reference signals in order to perform phase comparisons several times during one period of the reference signals.
However, the PLL circuit disclosed in this publication consumes electric power in large quantity since it has four frequency-dividers. Especially the consumption is large during an early stage when all the four phase comparators are operated for performing phase comparisons four times during one period of the reference signals. Furthermore, since the PLL circuit has the plurality of the phase comparators which require a relatively large layout space, there is a problem that it is difficult to implement the PLL circuit in an LSI.
Besides, the PLL circuit disclosed in the publication has the plurality of the phase comparators for comparing, with the outputs of the plurality of the frequency dividers that individually divide the frequency of the output of the voltage-controlled oscillator, the plurality of the reference signals having the frequency of 2.6 MHz and different phases which are produced by a delay circuit that delays an output of a fixed frequency divider having a frequency-division ratio of 5 for dividing by 5 the frequency of the output signal having the frequency of 13 MHz output from the reference oscillator.
In the PLL circuit of this type, the frequency of the plurality of the reference signals divided by the number of the reference signals has to match a channel spacing frequency, or a spacing in frequency of signals to be produced by the PLL circuit. However, in the PLL circuit disclosed in the publication, the number of the phase comparators in use, that is the number of the reference signals is an exponentiation of 2. For example, when the channel spacing frequency is required to be 200 kHz, if the number of 16 is selected as the exponentiation of 2, (the frequency of the reference signals)/(the number of the reference signals) is equal to 1300 kHz/5/16=162.5 kHz, and does not match the channel spacing frequency of 200 kHz.
When making (the frequency of the reference signals)/(the number of the reference signals) match a required channel spacing frequency is not possible, the frequency-division ratio of the frequency divider that divides the frequency of the output of the voltage-controlled oscillator may have to be of a value including not only an integer but also a fraction. In that case, however, C/N (Carrier to Noise Ratio) will be degraded since it is impossible to perform phase comparisons with high precision.
An object of the present invention is to provide a PLL circuit which has a short lock-up time and a low power consumption, and is easy to implement in an LSI for reducing the cost of manufacturing.
Another object of the present invention is to provide a PLL circuit which has a short lock-up time, and is capable of complying with any channel spacing frequency.
Another object of the present invention is to provide a PLL circuit which can perform phase comparisons with high precision even when its frequency divider has a frequency-division ratio of a value that includes not only an integer but also a fraction by which the output of its voltage-controlled oscillator is divided.
The PLL circuit according to the first embodiment of the invention comprises a PLL frequency synthesizer (13) including a first variable frequency-dividing means (8), and a second frequency-dividing means (9), a plurality of phase comparison signals (ER1 to ER13) being produced from outputs of the first and the second variable frequency-dividing means, at least one of the outputs of these variable frequency-dividing means being locked in phase accurately.
The second variable frequency-dividing means (9) may be formed from a variable frequency divider (10) and/or a counter (11).
The PLL circuit according to the first embodiment may include a producing means (2) for producing a plurality of reference signals (FR1 to FR13) having different phases, a voltage-controlled oscillator (6) and phase comparators (A1 to A13, B1 to B13), the first and the second variable frequency-dividing means (8, 9) dividing the frequency of the output signal of the voltage-controlled oscillator (6) to produce a plurality of feedback signal (FP1 to FP13), the phase comparators comparing the phases of the feedback signals with the phases of the reference signals to output the plurality of the phase comparison signals (ER1 to ER13)
It is possible that all of the phase comparison signals are output at the start, and a specific one of the phase comparison signals is output after near lock.
It is possible to cause the first and the second variable frequency-dividing means (8, 9) to operate at the start, and cause only the first variable frequency-dividing means (8) to continue to operate after near lock.
The PLL circuit according to the second embodiment of the invention comprises a producing means (2) including a reference oscillator (3) for producing a plurality of reference signal (FR1 to FR13) having different phases, a variable frequency-dividing means (8, 9) for dividing the frequency of an output signal of a voltage-controlled oscillator (6) to output a plurality of feedback signals (FP1 to FP13), and phase comparators (A1 to A13) for comparing the phases of the plurality of the reference signals with the phases of the plurality of the feedback signals, the number of the reference signals is set such that a quotient of (an oscillation frequency of the reference oscillator)/(a desired channel spacing frequency) is equal to the number of the reference signals.
A fixed frequency divider (4) may be provided between the reference oscillator (3) and the phase comparators (A1 to A13) so that the number of the reference signals can be set to a value (an integer) equal to the quotient divided by a frequency-division ratio of the fixed frequency divider.
The number of the phase comparators (A1 to A13) may be set to be equal to the above-described quotient or the above-described value.
By selecting one reference signal from among the plurality of the reference signals (FR1 to FR13) in succession, selecting one feedback signal from among the plurality of the feedback signals (FP1 to FP13) in succession, and comparing the phases of the selected signals, it is possible form the phase comparators as a single phase comparator.
The PLL circuit according to the third embodiment of the invention comprises a producing means (32) for producing a plurality of reference signals (FR1 to FR13) having different phases, a variable frequency-divider (59) for dividing the frequency of an output of a voltage-controlled oscillator (50) to produce feedback signals (FP1 to FP13), and phase comparators (37, 38) for comparing phases of the feedback signals with phases of the reference signals respectively to produce n (n being an integer equal to or larger than 2) phase comparison signals (U1 to U13, D1 to D13), the variable frequency-divider being supplied with frequency-division data according to n.
The variable frequency divider (59) may be constituted by a first variable frequency divider (51) and a second variable frequency divider (55), a PLL frequency synthesizer (45) including the first frequency divider may be provided, the first variable frequency divider may be supplied with frequency-division data N, and the second variable frequency divider may be supplied with frequency-division data N/n.
By outputting the plurality of the feedback signals (FP2 to FP13) from the second variable frequency divider (55) one by one in succession, outputting the plurality of the reference signals (FR2 to FR13) one by one in succession, and comparing the phases of the output signals, it is possible to deliver the plurality of the phase comparison signals (U2 to U13, D2 toD13).
The first variable frequency divider (51) and/or the second variable frequency divider (55) may be comprised of a pulse swallow counter (53, 57).
The PLL circuit according to the fourth embodiment of the invention comprises a producing means (62) for producing reference signals (FR1 to FR5), a variable frequency divider (71, 72) for dividing the frequency of an output of a voltage-controlled oscillator (70) by a frequency-division ratio of N+B/C (where N, B and C are integers, and Bxe2x89xa6C) to output feedback signals (FP1 to FP5), and phase comparators (65, 67) for comparing phases of the reference signals with phases of the feedback signals, phase comparisons being performed accurately one time out of C.
The variant of the fourth embodiment comprises a producing means (62) for producing a plurality of reference signals (FR1 to FR5) having different phases, a variable frequency divider (71, 72) for dividing the frequency of an output of a voltage-controlled oscillator (70) by a frequency-division ratio of N+B/C (where N, B and C are integers and Bxe2x89xa6C) to output a plurality of feedback signals (FP1 to FP5), phase comparators (65, 67) for comparing phases of the reference signals with phases of the feedback signals to output a plurality of phase comparison signals (U1 to U5, D1 to D5), phase comparisons being performed accurately one time out of C.
All the phase comparison signals (U1 to U5, D1 to D5) may be output at the start, and only the phase comparison signal (U1, D1) resulting from the accurate phase comparison may be output after near lock or after lock-up.
The frequency of the reference signal (FR1 to FR5) may be the same as the channel spacing frequency multiplied by C.